Yeah, RISC-V Is Actually a Good Design
Well-known people in the industry such as Dave Jaggar, Jim B. Keller and Dave Ditzel give RISC-V the thumbs up
The more I write about RISC-V the more realize how controversial RISC-V is in many circles. It is not uncommon to see claims that RISC-V is a bad design by RISC zealots trapped in the 1980s. The question is: How much stock should you actually put in random people on the internet making such claims?
Ideally, you should judge a design on its merits, but if that is not good enough for you, then perhaps you can respect the opinions of well-respected microprocessor designers. Here are a few of them making remarks on RISC-V.
Dave Jaggar - Arm Designer
Recently, Dave Jaggar gave a talk on the history of Arm Ltd. and their microprocessors. Who is Dave Jaggar you ask? Here is what wikipedia says:
David Jaggar (born 4 February 1967) is a computer scientist who was responsible for the development of the ARM architecture between 1992 and 2000, redefining it from a low-cost workstation processor to the dominant embedded system processor.
Jaggar did many important designs which contributed to the success of Arm. One essential choice, he was responsible for inventing compressed 16-bit instructions (Thumb) which made Arm a big success within the embedded space. Without Thumb Arm would never have made it into the Smartphone market. Arm got picked by Nokia because they gave dense code, high performance and low-power usage all in one package. That would have been impossible with compressed instructions. Interestingly, modern 64-bit Arm doesn't have compressed instructions, but it is an important part of RISC-V.
In his talk about Arm history, Dave Jaggar is asked what architecture to look into if you are interested in getting into microprocessors. Jaggar responds (51 minutes in):
Are there any ARM snipers? I would Google RISC-V and find out all about it. They have done a fine instruction-set, a fine job, and they are explaining it. Berkeley and Stanford are behind it. There are obviously commercial companies such as SiFive doing things, but it is the state-of-the-art for 32-bit general purpose instruction sets, and it's got the 16-bit compressed stuff.
Jim B. Keller - AMD, Apple, Tesla, and Intel Designer
Jim B. Keller is probably one of the best known microprocessor designers today, as he played a key role in the success of AMD and Apple. Let's quote wikipedia again:
James B. Keller (born 1958/1959) is a microprocessor engineer best known for his work at AMD and Apple. He was the lead architect of the AMD K8 microarchitecture (including the original Athlon 64) and was involved in designing the Athlon (K7) and Apple A4/A5 processors. He was also the coauthor of the specifications for the x86-64 instruction set and HyperTransport interconnect. From 2012 to 2015, he returned to AMD to work on the AMD K12 and Zen microarchitectures.
Chips used in important Apple products like iPhone 4, iPad, and iPad 2 were designed by Keller. In this interview at TechTechPotato on Arm vs x86 vs RISC-V he has this to say:
Now, RISC-V shows up. It is the shiny new cousin right, because there's no legacy and its actually an open instruction-set architecture and people build in universities where they didn't have time or interest to add too much junk like some architectures have, so relatively speaking because of its pedigree and age, it is early in the life cycle of complexity and it is a pretty good instruction-set. They did a fine job, so if I was just going to say I want to build a computer really fast and I want it to go fast, RISC-V is the easiest one. It has got all the right features. It has all the right top eight instructions. The ones you actually need to optimize. It doesn't have too much junk.
The eight instructions Kelly is alluding to is earlier in the interview where he is remarking on how most of the time a microprocessor is executing only one out of eight frequently used instructions such as load, store, branch, add etc.
Dave Ditzel - Transmeta, RISC, Esperanto
Dave Ditzel is known for thinking outside the box. Let me quote EE Journalto introduce him:
At Bell Labs, Ditzel also co-authored the foundational RISC document, “The Case for the Reduced Instruction Set Computer,” with UC Berkeley’s Professor David Patterson. Ditzel then joined Sun Microsystems as CTO of the SPARC Technology Business, where he led development of the SPARC RISC processor architecture and the 64-bit SPARC ISA. Oracle bought Sun Microsystems in 2010 and later discontinued corporate SPARC development in 2016. But thanks to SPARC International, the SPARC ISA continues, as fully open, non-proprietary, royalty-free IP.
Some of you may remember Transmeta, which was founded in 1995 by Ditzel. It was a hot topic in the early 2000s with the Crusoe processor, which many believed would unseat x86. It was based on the idea of Very Long Instruction Word (VLIW), where the compiler bundled instructions which could be executed in parallel for increased performance. The idea was also that Transmeta chips could emulate any ISA including x86.
Read more about VLIW: Very Long Instruction Word Microprocessors
Anyway, my point is that Ditzel has a history of thinking outside the box. When starting Esperanto Technologies, him and his processor designers looked at creating these custom chips for accelerating AI. They developed their own instruction-set for these chips but realized a lot of investment would be needed in tooling and other infrastructure and thus began looking at RISC-V. Through a series of internal tests they came to the conclusion that RISC-V was actually a very well-designed ISA which they could use to build their ET-SOC-1 inference engine.
Do Your Own Comparisons
Thanks to Godbolt, it is easy to quickly make comparisons of various instruction-set architectures. Many people will make these small assembly code snippets to argue that RISC-V is a bad design which requires many times more instructions than comparable architectures. Yet, this does not pan out once you look beyond toy examples of 4-5 assembly opcodes.
// C - Most basic sorting algorithm
void bubble_sort(int xs[], int n) {
for (int i = 0; i < n - 1; i++) {
for (int j = 0; j < n - i - 1; j++) {
// swap values if not in order
if (xs[j] > xs[j + 1]) {
int temp = xs[j];
xs[j] = xs[j + 1];
xs[j + 1] = temp;
}
}
}
}
We can compare the RISC-V, Arm and x86 assembly code for this basic code in Godbolt. I tried with gcc 10.2.0 with the which was somewhat arbitrarily chosen, and I got the following results with the -Os
switch which optimizes for small code.
RV32gc (RISC-V 32-bit) - 24 lines of code
ARM 32-bit - 25 lines of code
x86-64 - 26 lines of code
POWER (IBM RISC ISA) - 32 lines of code
It may be argued that we should compare with newer architectures like the 64-bit Arm instruction-set. We can do that. Yet, this makes no difference on the code count. Strangely it adds another line to the RISC-V code, but that line is utterly pointless. The follow RISC-V assembly at the beginning for RV32gc gets rewritten:
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